1. Field of the Invention
The present invention relates to semiconductor technology, and specifically to MOS non-volatile memory technology. More particularly, the present invention relates to MOS non-volatile memory cells having reduced operation disturb and to methods for fabricating such memory cells.
2. Description of Related Art
Operation mode disturb is an issue in push-pull memory cell designs. Such designs include a non-volatile n-channel floating gate memory transistor and a non-volatile p-channel floating gate memory transistor connected in series between a high column line (CLH) and a low column line (CLL). During normal operation of the memory containing the memory cell, CLH is coupled to VDD and CLL is coupled to ground. FIG. 1A shows a typical push-pull memory cell design including a p-channel non-volatile transistor in series with an n-channel non-volatile transistor driving a switch device (shown as a volatile n-channel transistor having its gate connected to the common drain connection of the n-channel floating gate transistor and the p-channel floating gate transistor). The memory cell is programmed (or erased) such that only one of the two memory transistors is turned on and the other transistor remains off. When the p-channel memory transistor is turned off and the n-channel memory transistor is turned on, the output of the memory cell is “low” and is near ground. When the p-channel memory transistor is turned on and the n-channel memory transistor is turned off, the output of the memory cell is “high” and is near VDD.
Operation mode disturb occurs during normal operation of the memory array. When the n-channel memory transistor is turned off and the p-channel memory transistor is turned on, the n-channel memory transistor is subject to a drain edge stress because the common drain connection of the p-channel memory transistor and the n-channel memory transistor is at VDD potential. This stress, which occurs over the lifetime of the device, will cause the n-channel transistor to lose electrons and eventually begin to turn on. When the memory device is used as a configuration memory in a user-programmable logic device, this action will begin to turn off the configuration switch device connected to the memory cell.
When the p-channel memory transistor is turned off and the n-channel memory transistor is turned on, the p-channel memory transistor is subject to a drain edge stress because the common drain connection of the p-channel memory transistor and the n-channel memory transistor is at ground potential. This stress, which occurs over the lifetime of the device, will cause the p-channel transistor to lose electrons and eventually begin to turn on. The p-channel case is worse than the n-channel case because hot electrons are more easily transported through the gate oxide of the memory transistor than are holes. When the memory device is used as a configuration memory in a user-programmable logic device, this action will begin to turn on the configuration switch device connected to the memory cell.
Either of the above-described conditions will eventually result in product functional failure. Existing solutions involve adding a p-channel volatile transistor in series with the p-channel memory transistor. An n-channel volatile transistor can also be added in series with the n-channel memory transistor. Such a configuration with both an n-channel volatile transistor and a p-channel volatile transistor is shown in FIG. 1B. During read mode, both the n-channel volatile transistor and the p-channel volatile transistor are turned on. The solution implemented by the circuit of FIG. 1B significantly adds to the size of the memory cell and increases the metal line overhead for the memory array.